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technical note double-cell memory for plug & play ddr/ddr2 (for memory module) spd memory br34e02-w description br34e02fvt-w is 256 8 bit electrically erasable prom (based on serial presence detect) features ? 256 8 bit architecture serial eeprom ? wide operating voltage range: 1.7v-3.6v ? two-wire serial interface ? high reliability connection using au pads and au wires ? self-timed erase and write cycle ? page write function (16byte) ? write protect mode settable reversible write protect function: 00h-7fh write protect 1 (onetime rom) : 00h-7fh write protect 2 (hardwire wp pin) : 00h-ffh ? low power consumption write (at 1.7v ) : 0.4ma (typ.) read (at 1.7v ) : 0.1ma(typ.) standby ( at 1.7v ) : 0.1 a(typ.) ? data security write protect feature (wp pin) inhibit to write at low v cc ? compact package: tssop-b8, vson008x2030 ? high reliability fine pattern cmos technology ? rewriting possible up to 1,000,000 times ? data retention: 40 years ? noise reduction filtered inputs in scl / sda ? initial data ffh at all addresses br34e02-w series capacity bit format type power source voltage tssop-b8 vson008x2030 2kbit 256x8 br34e02-w 1.7v 3.6v ver.a aug.2007
2/19 absolute maximum ratings (ta=25 ) parameter symbol rating unit supply voltage v cc -0.3 +6.5 v 330(br34e02fvt-w) *1 power dissipation pd 300(br34e02nux-w) *2 mw storage temperature tstg -65 +125 operating temperature topr -40 +85 terminal voltage (a0) - -0.3 10.0 v terminal voltage (etcetera) - -0.3 v cc +0.3 v * reduce by 3.3mw(*1), 3.0 mw(*2)/ c over 25 c recommended operating conditions parameter symbol rating unit supply voltage v cc 1.7 3.6 v input voltage in 0 v cc v memory cell characteristics ta=25 , v cc =1.7v 3.6v specification parameter min. typ. max. unit write / erase cycle *1 1,000,000 cycles data retention *1 40 years *1:not 100% tested electrical characteristics - dc unless otherwise specified ta=-40 +85 , v cc =1.7v 3.6v specification parameter symbol min. typ. max. unit test condition "h" input voltage vih1 0.7 v cc - vcc+0.3 v "l" input voltage vil1 - - 0.3 v cc v "l" output voltage 1 vol1 -0.3 - 0.4 v iol=2.1ma 2.5v Q v cc Q 3.6v sda "l" output voltage 2 vol2 - - 0.2 v iol=0.7ma 1.7v Q v cc 2.5v sda input leakage current 1 ili1 -1 - 1 a vin=0v v cc a0,a1,a2,scl input leakage current 2 ili2 -1 - 15 a vin=0v v cc wp input leakage current 3 ili3 -1 - 20 a vin=vhv(a0) output leakage current ilo -1 - 1 a vout=0v v cc icc1 - - 1.0 ma v cc =1.7v,fscl=100 hz twr=5ms byte write page write write protect icc2 - - 3.0 ma v cc =3.6v,fscl=100 hz, twr=5ms byte write page write write protect operating current icc3 - - 0.5 ma v cc =3.6v,fscl=100 hz random read current read sequential read standby current isb - - 2.0 a v cc =3.6v,sda,scl= v cc a0,a1,a2=gnd,wp=gnd a0 hv voltage vhv 7 - 10 v vhv-vcc R 4.8v note: this ic is not designed to be radiation-resistant.
3/19 sda (in) scl sda (out) t hd :sta t hd :dat t su :dat t buf t pd t dh t low t high t r t f sda scl t su :sta t su :sto t hd :sta start bit stop bi t sda scl d0 ack stop condition start condition t wr write data(n) fig.1-(a) synchronous data timing fig.1-(b) start/stop bit timing fig.1-(c) write cycle timing sda data is latched into the chip at the rising edge of scl clock. output data toggles at t he falling edge of scl clock. fig.1-(d) wp timing of the write operation scl wp scl wp fig.1-(e) wp timing of the write cancel operation for write operation, wp must be "low" from the rising edge of the clock (which takes in d0 of first byte) until the end of twr. (see fig.1-(d) ) during this period, write operation can be canceled by setting wp "high". see fig.1-(e) when wp is set to "high" during twr, write operation is immediately ceased, making the data unreliable. it must then be re-written. electrical characteristics - ac unless otherwise specified ta=-40 +85 , v cc =1.7v 3.6v fast-mode 2.5v Q v cc Q 5.5v standard-mode 1.7v Q v cc Q 5.5v parameter symbol min. typ. max. min. typ. max. unit clock frequency fscl 400 100 khz data clock high period thigh 0.6 4.0 s data clock low period tlow 1.2 4.7 s sda and scl rise time *1 tr 0.3 1.0 s sda and scl fall time *1 tf 0.3 0.3 s start condition hold time thd:sta 0.6 4.0 s start condition setup time tsu:sta 0.6 4.7 s input data hold time thd:dat 0 0 ns input data setup time tsu:dat 100 250 ns output data delay time tpd 0.1 0.9 0.1 3.5 s output data hold time tdh 0.1 0.1 s stop condition setup time tsu:sto 0.6 4.0 s bus free time tbuf 1.2 4.7 s write cycle time twr 5 5 ms noise spike width (sda and scl) ti 0.1 0.1 s wp hold time thd wp 0 0 ns wp setup time tsu wp 0.1 0.1 s wp high period thigh wp 1.0 1.0 s *1 not 100 tested fast / standard modes fast mode and standard mode differ only in operation frequency. operations performed at 100khz are considered in "standard-mode", while those conduct ed at 400khz are in "fast-mode". please note that these clock frequencies are maximum values. at lower power supply voltage it is difficult to operate at high speeds. the eeprom can operate at 400khz, between 2.5v and 3.6v, and at 100khz from 1.7v-2.5v. synchronous data timing t wr high : wp sda data(n) wp stop bit d1 d0 ack ack data(1) data(n) t su wp t wr sda d0 ack ack d1 data(1)
4/19 *1 open drain output requires a pull-up resistor. *2 wp pin has a pull-down resistor . please leave unconnected or connect to gnd when not in use. fig.7 "l" output voltage vol2-iol2 (v cc =1.7v) 8 7 6 5 4 3 2 1 sda scl wp v cc gnd a2 a1 a0 address decoder slave , word address register data register contorol logic high voltage gen. v cc level detect 8bit 8bit 8bit ack start stop protect_memory_arry 2kbit_memory_arry block diagram pinout diagram and description pin name input/output functions v cc power supply gnd ground 0v a0,a1,a2 in slave address set. scl in serial clock input sda in / out slave and word address, *1 serial data input, seri al data output wp in write protect input *2 electrical characteristics curves the following characteristic data are typ. value. fig.6 "l" output voltage vol1-iol1 (v cc =2.5v) fig.8 input leakage current ili1 (a0,a1,a2,scl,sda) fig.9 input leakage current ili2 (wp) 8 7 6 5 1 2 3 4 v cc wp scl sda a 0 a 1 a 2 gnd fig.3 pin configuration br34e02fvt-w br34e02nux-w fig.5 "l" input voltage vil (a0,a1,a2,scl,sda,wp) fig.4 "h" input voltage vih (a0,a1,a2,scl,sda,wp) fig.2 block diagram 0 0.2 0.4 0.6 0.8 1 01 234 iol1[ma] vol1[v] ta=85 spec ta=25 ta=-40 0 1 2 3 4 5 6 01 234 vcc[v] vih1,2[v] spec ta=85 ta=-40 ta=25 0 1 2 3 4 5 6 01234 vcc[v] vil1,2[v] ta=85 ta=-40 ta=25 spec 0 0.2 0.4 0.6 0.8 1 01 234 iol2[ma] vol2[v] ta=85 spec ta=25 ta=-40 0 0.2 0.4 0.6 0.8 1 1.2 01 234 vcc[v] ili1[ a] ta=85 ta=25 ta=-40 spec 0 4 8 12 16 01234 vcc[v] ili2[a] ta=85 ta=25 ta=-40 spec
5/19 fig.10 write operating current icc1,2 (fscl=100khz,400khz) fig.15 data clock low period tlow fig.11 read operating current icc3 (fscl=400khz) fig.13 clock frequency fscl fig.17 start condition setup time tsu:sta fig.12 standby current isb fig.14 data clock high period thigh fig.19 data hold time thd:dat(low) fig.21 input data setup time tsu:dat(low) fig.16 start condition hold time thd:sta 0 0.1 0.2 0.3 0.4 0.5 0.6 01234 vcc[v] icc3[ma] ta=-40 spec ta=85 ta=25 =100khz data=aah 0 0.5 1 1.5 2 2.5 3 3.5 01234 vcc[v] icc1,2[ma] spec1 spec2 scl=400khz(v cc R2.5v) fscl=100khz(1.7vQvccv) data=aa ta=25 ta=85 ta=-40 0 0.5 1 1.5 2 2.5 01234 vcc[v] isb[a] ta=-40 spec ta=85 ta=25 0 1 2 3 4 5 01234 vcc[v] thigh[s] ta=-40 spec2 ta=85 ta=25 spec1 spec1:fast-mode spec2:standard-mode 1 10 100 1000 10000 01234 vcc[v] fscl[khz] ta=-40 spec1 ta=85 ta=25 spec2 spec1:fast-mode spec2:standard-mode 0 1 2 3 4 5 01234 vcc[v] tlow[s] spec2 ta=-40 ta=85 ta=25 spec1 spec1:fast-mode spec2:standard-mode fig.18 data hold time thd:dat(high) -200 -150 -100 -50 0 50 01234 vcc[v] thd:dat(high)[s] spec1,2 ta=-40 ta=85 ta=25 spec1:fast-mode spec2:standard-mode 0 1 2 3 4 5 01234 vcc[v] thd:sta[s] ta=-40 spec2 ta=85 ta=25 spec1 spec1:fast-mode spec2:standard-mode 0 1 2 3 4 5 01234 vcc[v] tsu:sta[s] ta=-40 spec2 ta=85 ta=25 spec1 spec1:fast-mode spec2:standard-mode -200 -100 0 100 200 300 01234 vcc[v] tsu:dat(high)[ns] spec1 ta=85 ta=-40 ta=25 spec1:fast-mode spec2:standard-mode -200 -100 0 100 200 300 01234 vcc[v] tsu:dat(low)[ns] spec2 ta=85 ta=-40 ta=25 spec1:fast-mode spec2:standard-mode -200 -150 -100 -50 0 50 01234 vcc[v] thd:dat(low)[s] spec1,2 ta=-40 ta=85 ta=25 spec1:fast-mode spec2:standard-mode fig.20 input data setup time tsu:dat(high)
6/19 fig.24 stop condition setup time tsu:sto fig.25 bus free time tbuf fig.26 write cycle time twr fig.31 wp setup time tsu:wp fig.32 wp high period thigh:wp fig.30 noise spike width ti(sda l) fig.23 output data hold time tdh fig.22 output data delay time tpd fig.29 noise spike width ti(sda h) fig.27 noise spike width ti(scl h) fig.28 noise spike width ti(scl l) 0 1 2 3 4 01234 vcc[v] tdh[ s] ta=85 ta=-40 ta=25 spec1 spec2 spec1:fast-mode spec2:standard-mode 0 1 2 3 4 01234 vcc[v] tpd[ s ] spec2 ta=85 ta=-40 ta=25 spec1 spec1 spec2 spec1:fast-mode spec2:standard-mode 0 1 2 3 4 5 01234 vcc[v] tsu:sto[s] spec2 ta=85 ta=-40 spec1 spec1:fast-mode spec2:standard-mode 0 1 2 3 4 5 01234 vcc[v] tbuf[s] spec2 ta=85 ta=-40 ta=25 spec1 spec1:fast-mode spec2:standard-mode 0 1 2 3 4 5 6 01234 vcc[v] twr[ms] spec1,2 ta=85 ta=-40 ta=25 spec1:fast-mode spec2:standard-mode 0 0.1 0.2 0.3 0.4 0.5 0.6 01234 vcc[v] ti(scl h)[ s] spec1,2 ta=85 ta=-40 ta=25 spec1:fast-mode spec2:standard-mode 0 0.1 0.2 0.3 0.4 0.5 0.6 01234 vcc[v] ti(scl l)[ s] spec1,2 ta=85 ta=-40 ta=25 spec1:fast-mode spec2:standard-mode 0 0.1 0.2 0.3 0.4 0.5 0.6 01234 vcc[v] ti(sda h)[ s] spec1,2 ta=85 ta=-40 ta=25 spec1:fast-mode spec2:standard-mode 0 0.1 0.2 0.3 0.4 0.5 0.6 01234 vcc[v] ti(sda l)[ s] spec1,2 ta=85 ta=-40 ta=25 spec1:fast-mode spec2:standard-mode -0.6 -0.4 -0.2 0 0.2 01234 vcc[v] tsu:wp[ s] spec1,2 ta=85 ta=-40 ta=25 spec1:fast-mode spec2:standard-mode 0 0.2 0.4 0.6 0.8 1 1.2 01234 vcc[v] thigh:wp[ s] spec1,2 ta=85 ta=-40 ta=25 spec1:fast-mode spec2:standard-mode
7/19 data transfer on the i 2 c bus data transfer on the i 2 c bus the bus is considered to be busy after the start condition and free a certain time after the stop condition. every sda byte must be 8-bits long and requires an ackn owledge signal after each byte. the devices have master and slave configurations. the master device initiates an d ends data transfer on the bus and generates the clock signals in order to permit transfer. the eeprom in a slave configuration is controlled by a unique address. devi ces transmitting data are referred to as the transmitter. the devices receiv ing the data are called receiver. start condition (recognition of the start bit) ? all commands are proceeded by the start condition, which is a high to low transition of sda when scl is high. ? the device continuously monitors the sda and scl lines for t he start condition and will not respond to any command until this condition has been met. (see fig.1-(b) start/stop bit timing) stop condition (recognition of stop bit) ? all communications must be terminated by a stop conditi on, which is a low to high transition of sda when scl is high. (see fig.1-(b) start/stop bit timing) write protect by soft ware ? set write protect command and permanent set write protect command set data of 00h 7fh in 256 words write protection block. clear write protect command can cancel write protection blo ck which is set by set write protect command. cancel of write protection block which is set by permanent set write protect command at once is impossibility. when these commands are carried out, wp pin must be open or gnd. acknowledge ? acknowledge is a software used to indicate successful data transfers. the transmitter device will release the bus after transmitting eight bits. when inputting the slave addre ss during write or read operati on, the transmitter is the -com. when outputting the data during read operation, the transmitter is the eeprom. ? during the ninth clock cycle the receiver will pull the sda line low to verify that the eight bits of data have been received. (when inputting the slave address during writ e or read operation, eeprom is the receiver. when outputting the data during read operation the receiver is the -com.) ? the device will respond with an acknowledge after recognit ion of a start condition and its slave address (8bit). ? in write mode, the device will respond with an acknowledge after the receipt of each subsequent 8-bit word (word address and write data). ? in read mode, the device will transmit eight bits of data, release the sda line, and monitor the line for an acknowledge. ? if an acknowledge is detected and no stop condition is generat ed by the master, the device will continue to transmit the data. if an acknowledge is not det ected, the device will terminate further data transmissions and await a stop condition before returning to standby mode. device addressing ? following a start condition, the master outputs the slave address to be accessed. the most significant four bits of the slave address are the ?device type indentifier.? for th is eeprom it is ?1010.? (for wp register access this code is "0110".) ? the next three bits identify the spec ified device on the bus (device address) . the device address is defined by the state of the a0,a1 and a2 input pins. this ic works only when the device address input from the sda pin corresponds to the status of the a0,a1 and a2 input pins. using this address scheme allows up to eight devices to be connected to the bus.
8/19 ? the last bit of the stream (r/w read/write) determines the operation to be performed. r/w=0 ???? write (including word address input of random read) r/w=1 ???? read slave address set pin device type device address read write mode access area a2 a1 a0 1010 a2 a1 a0 r/w 2kbit access to memory a2 a1 a0 a2 a1 a0 r/w access to permanent set write protect memory gnd gnd vhv 0 0 1 r/w access to set write protect memroy gnd vcc vhv 0110 0 1 1 r/w access to clear write protect memory write protect pin(wp) when wp pin set to vcc (h level), write protect is set for 256 words (all address). when wp pin set to gnd (l level), it is enable to write 256 words (all address). if permanent protection is done by writ e protect command, lower half area (00 7fh address) is inhibited writing regardless of wp pin state. wp pin has a pull-down resistor. please be left unconnect ed or connect to gnd when wp feature is not in use. confirm write protect resistor by ack according to state of write protect resistor, ack is as follows. state of write protect registor wp input input command ack address ack data ack write cycle(twr) pswp, swp, cwp no ack - no ack no ack no in case, protect by pswp - page or byte write (00 7fh) ack wa7 wa0 ack d7 d0 no ack no swp no ack - no ack - no ack no cwp ack - ack - ack yes pswp ack - ack - ack yes 0 page or byte write (00 7fh) ack wa7 wa0 ack d7 d0 no ack no swp no ack - no ack - no ack no csp ack - ack - no ack no pswp ack - ack - no ack no in case, protect by swp 1 page or byte write ack wa7 wa0 ack d7 d0 no ack no pswp, swp, cwp ack - ack - ack yes 0 page or byte write ack wa7 wa0 ack d7 d0 ack yes pswp, swp, cwp ack - ack - no ack no in case, not protect 1 page or byte write ack wa7 wa0 ack d7 d0 no ack no - is don?t care state of write protect registor command ack address ack data ack in case, protect by pswp pswp, swp, cwp no ack - no ack - no ack swp no ack - no ack - no ack cwp ack - no ack - no ack in case, protect by swp pswp ack - no ack - no ack in case, not protect pswp, swp, cwp ack - no ack - no ack
9/19 w r i t e s t a r t r / w a c k s t o p word address(n) data(n) sda line a c k a c k data(n+15) a c k slave address 1 0 0 1a0 a1 a2 wa 7 d0 d7 d0 wa 0 command write cycle during write cycle operation data is wr itten in the eeprom. the byte write cy cle is used to write only one byte. in the case of writing continuous data consisting of more t han one byte, page write is used. the maximum bytes that can be written at one time is 16 bytes. ? with this command the data is programmed into the indicated word address. ? when the master generates a stop conditi on, the device begins the internal wr ite cycle to the nonvolatile memory array. ? once programming is started no commands are accepted for twr (5ms max.). ? this device is capable of sixteen-byte page write operations. ? if the master transmits more than sixteen words prior to gen erating the stop condition, t he address counter will ?roll over? and the previously transmitted data will be overwritten. ? when two or more byte of data are input, the four low order address bits are internally incremented by one after the receipt of each word, while the four higher order bits of the address (wa7 wa4) remain constant. a1 a2 wa 7 d7 11 00 w r i t e s t a r t r / w s t o p word address dat a slave address a0 wa 0 d0 a c k sda line a c k a c k fig.33 byte write cycle timing fig.34 page write cycle timing
10/19 command read cycle during read cycle operation data is read from the eeprom. the read cycle is composed of random read cycle and current read cycle. the random read cycle re ads the data in the indicated address. the current read cycle reads the data in the internally i ndicated address and verifies the data immediately after the write operation. the sequential read operation can be performed with both cu rrent read and random read. with the sequential read cycle it is possible to continuously read the next data. ? random read operation allows the master to access any memory location indicated by word address. ? in cases where the previous operation is random or cu rrent read (which includes sequential read), the internal address counter is increased by one from the last access ed address (n). thus current read outputs the data of the next word address (n+1). ? if an acknowledge is detected and no stop condition is generated by the master ( -com), the device will continue to transmit data. (it can transmit all data (2kbit 256word)) ? if an acknowledge is not detected, t he device will terminate further data transmi ssions and await a stop condition before returning to standby mode. ? if an acknowledge is detected with the "low" level (not "high" level), the command will become sequential read, and the next data will be transmitt ed. therefore, the read comm and is not terminated. in order to terminate read input acknowledge with "high" always, then input a stop condition. it is necessary to input ?high? at last ack timing. a1 a2 d7 11 00 r e a d s t a r t r / w s t o p dat a sda line slave address a0 d0 a c k a c k fig.36 current read cycle timing it is necessary to input ?high? at last ack timing. fig.37 sequential read cycle timing with current read fig.35 random read cycle timing w r i t e s t a r t r / w a c k s t o p word address(n) sda line a c k a c k data(n) a c k slave address 10 0 1a0 a1 a2 wa 7 a0 d0 slave address 10 0 1a1 a2 s t a r t d7 r / w r e a d wa 0 r e a d s t a r t r / w a c k s t o p data(n) sda line a c k a c k data(n+x) a c k slave address 10 0 1a0 a1 a2 d0 d7 d0 d7 it is necessary to input ?high? at last ack timing.
11/19 write protect cycle ? permanent set write protect command set data of 00h 7fh in 256 words write protecti on block. clear write protect command can cancel write protection block which is set by set write protect command. c ancel of write protection block which is set by permanent set write protect co mmand at once is impossibilit y. when these commands are carried out, wp pin must be open or gnd. ? permanent set write protect command needs twr from st op condition same as byet e write and page write, during twr, input command is canceled. ? refer to p8/19 about reply of ack in each protect state. ? permanent set write protect command set data of 00h 7fh in 256 words write protecti on block. clear write protect command can cancel write protection block which is set by set write protect command. c ancel of write protection block which is set by permanent set write protect co mmand at once is impossibilit y. when these commands are carried out, wp pin must be open or gnd. ? permanent set protect command needs twr from stop condition same as byete write and page write, during twr, input command is canceled. ? refer to p8/19 about reply of ack in each protect state. w r i t e s t a r t r / w a c k s t o p word address sda line a c k data a c k slave address 1 0 0 1a0 a1 a2 * * * * wp *:don?t care w r i t e s t a r t r / w a c k s t o p word address sda line a c k data a c k slave address 1 00 11 0 0 * * * * wp *:don?t care fig. 38 permanent write protect cycle fi g . 39 set write protect c y cle
12/19 ? clear write protect command can cancel write protection block which is set by set write protect command. cancel of write protection block which is set by permanent set write protect command at once is impossibility. when these commands are carried out, wp pin must be open or gnd. ? permanent clear write protect command needs twr from stop condition same as byete write and page write, during twr, input command is canceled. ? refer to p8/19 about reply of ack in each protect state. software reset execute software reset in the event t hat the device is in an unexpected stat e after power up and/or the command input needs to be reset. below are three types fig.39 ?(a), (b), (c) of software reset: during dummy clock, release the sda bus (tied to v cc by a pull-up resistor). during this time the device may pull the sda line low for acknowledge or the outputting of read data.if the master sets the sda li ne to high, it will conflict with the device output low, which can cause current overload and re sult in instantaneous power down, which may damage the device. 1 2 13 14 scl dummy clock 14 start 2 scl scl fig.39-(a) dummy clock 14 + start+start 1 2 3 8 9 7 fig.39-(c) start 9 * command starts with start condition. 2 1 8 9 dummy clock 9 start fig.39-(b) start + dummy clock 9 + start start command command command command command command start 9 sda sda sda w r i t e s t a r t r / w a c k s t o p word address sda line a c k data a c k slave address 1 00 11 1 0 * * * * wp *:don?t care fi g . 40 clear write protect c y cle
13/19 an enlargement ?the rising edge ? of sda wp cancellation effective period slave address slave address write command slave data address word address slave address s t a r t s o p a c k h s t a r t s t a r t a c k h s t a r t a c k h s t a r t a c k l a c k l a c k l s o p after the internal write cycle is completed, ack will be returned (ack=low). then input next word address and data. during the internal write cycle, no ack will be returned. (ack=high) ??? acknowledge polling since the ic ignores all input commands during the inte rnal write cycle, no ack signal will be returned. when the master sends the next command after the write command, if the device returns an ac k signal it means that the program is completed. no ack signal indicates that the device is still busy. using acknowledge polling decreases the waiting time by twr=5ms. when operating write or current read af ter write, first transmit the slave addre ss (r/w is"high" or "low"). after the device returns the ack signal continue word address input or data output. wp effective timing wp is normally fixed at "h" or "l". however, in case wp nee ds to be controlled in order to cancel the write command, pay attention to ?wp effective timing? as follows: the write command is canceled by setting wp to "h " within the wp cancellation effective period. the period from the start condition to the rising edge of the clo ck (which takes in the data do - the first byte of the page write data) is the ?invalid cancellation period?. wp input is considered inconsequential during this period. the setup time for the rising edge of the scl, which takes in do, must be more than 100ns. the period from the rising edge of scl (which takes in the data d0 ) to the end of internal write cycle (twr) is the ?effective cancellation period?. when wp is set to "h" during twr, wr ite operation is stopped, making it necessary to rewrite the data. it is not necessary to wait for twr (5ms max.) after stopping the write command by wp because the device is in standby mode. ? the rising edge of the clock which take in d0 scl d0 ack an enlargement scl sda ack d0 sda wp wp cancellation invalid period data is not guaranteed no data will be written stop of the write operation fig.41 wp effective timing slave address d7 d6 d5 d4 d3 d2 d1 d0 data twr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address the first write command twr the second write command ??? twr fig.40 successive write operation by acknowledge polling
14/19 microcontroller the capacitance of bus line (cbus) fig.43 i/o circuit command cancellation from the start and stop conditions command input is canceled by successive inputs of start and stop conditions. (refer to fig.42) however, during ack or data output, the device may set th e sda line to low, making operation of the start and stop conditions impossible, and thus preventing reset. in this case execute reset by software. (refer to fig.39) the internal address counter will not be determined when operating the cancel command by the start and stop conditions during random, sequential or current read. operate a random read in this case. i/o circuit sda pin pull-up resistor a pull-up resistor is required because sda is an nm os open drain. determine the resistor value of (r pu ) by considering the vil and il, and vol-iol characteristics. if a large r pu is chosen, the clock frequency needs to be slow. a smaller r pu will result in a larger operating current. maximum r pu the maximum of r pu can be determined by the following factors. the sda rise time determined by r pu and the capacitance of the bus line(cbus) must be less than tr. in addition, all other timings must be kept within the ac specifications. when the sda bus is high, the voltage a at the sda bus is determined from the total input leakage(il) of all devices connected to the bus. r pu must be higher than the input high level of the microcontroller and the device, including a noise margin 0.2v cc . v cc -i l r pu -0.2 v cc R vih r pu Q 0.8v cc -v ih il examples: when v cc =3v, il=10 a, vih=0.7 v cc according to Q 300 k ? r pu Q 0.83-0.73 1010 -6 fig.42 command cancellation by the start and stop conditions during input of the slave address scl sda 1 1 0 0 start condition stop condition r pu a br34e02 sda pin il il
15/19 fig.45 input/output collision timing minimum r pu the minimum value of r pu is determined by following factors. meets the condition that v olmax =0.4v, i olmax =3ma when the output is low. v olmax =0.4v must be lower than the input low le vel of the microcontroller and the eeprom including the recommended noise margin of 0.1v cc . v olmax Q vil-0.1 v cc examples: v cc =3v, vol=0.4v, iol=3ma, the vil of the controller and the eeprom is vil=0.3v cc , and v ol =0.4 v and v il =0.3 3 =0.9 v so that condition is met scl pin pull-up resistor when scl is controlled by the cmos output t he pull-up resistor at scl is not required. however, should scl be set to hi-z, connection of a pull-up resistor between scl and v cc is recommended. several k ? are recommended for the pull-up resistor in order to drive the output port of the microcontroller. a0, a1, a2, wp pin connections device address pin (a0, a1, a2) connections the status of the device address pins is compared with the device address sent by the master. one of t he devices that is connected to the identical bus is selected. pu ll up or down these pins or connect them to v cc or gnd. pins that are not used as device address (n.c.pins) may be high, low, or hi-z. wp pin connection the wp input allows or prohibits write operations. when wp is high, only read is available and write to all address is prohibited. both read and write are available when wp is low. in the event that the device is used as a rom, it is recommended t hat the wp input be pulled up or connected to v cc . when both read and write are operated, the wp input must be pulled down or connect ed to gnd or controlled. microcontroller connection concerning rs the open drain interface is recommended for the sda port in the i 2 c bus. however, if the tr i-state cmos interface is applied to sda, insert a series resistor (rs) between the sda pin of the device and the pull up resistor r pu is recommended, since it will serve to limit the current betw een the pmos of the microcont roller, and the nmos of the eeprom. rs also protects the sda pin from surges. therefore, rs is able to be used though open drain inout of the sda port. R 867 ? r pu R 3-0.4 310 -3 according to a ck ?l? output of eeprom 'h'output of controller the ?h? output of controller and the ?l? output of eeprom may cause current overload to sda line. scl sda v cc -v ol r pu Q i ol r pu R v cc -v ol i ol r pu controller r s eeprom fig.44 i/o circuit
16/19 vcc r s vcc i R 300 ? r s R 3 1010 -3 examples: when v cc =3v, i=10ma Q i r s R controller eeprom "l" output r s r pu "h" output maximum current rs maximum the maximum value of rs is determined by following factors. sda rise time determined by r pu and the capacitance value of the bus li ne (cbus) of sda must be less than tr. in addition, the other timings must be with in the timing conditions of the ac. when the output from sda is low, the volt age of the bus at a is determined by r pu, and rs must be lower than the input low level of the microcontroller, including recommended noise margin (0.1v cc ). rs minimum the minimum value of rs is determined by the current overload during bus conflict. current overload may cause noises in the power line and instantaneous power down. the following conditions must be met, where ?i? is the maximum permissible current, which depends on the vcc line impedance as well as other factors. ?i? current must be less than 10ma for eeprom. Q r pu v ol +0.1v cc Q v il (v cc -v ol )r s + r s Q 1.67 k ? r pu +r s Q v il -v ol -0.1v cc 1.1v cc -v il 1.13-0.33 0.33-0.4-0.13 according to r s examples : when v cc =3v v il =0.3v cc v ol =0.4v r pu =20k ? 2010 3 r pu controller r s eeprom i ol a bus capacitance v ol v cc v il fig.46 i/o circuit fig.47 i/o circuit
17/19 i 2 c bus input / output equivalent circuits input (a0,a2,scl) input / output (sda) input (a1) input (wp) fig.48 input pin circuit fig.50 input pin circuit fig.49 input / output pin circuit fig.51 input pin circuit
18/19 power supply notes v cc increases through the low voltage region where the internal circuit of ic and the microcontroller are unstable. in order to prevent malfunction, the ic has p.o.r and lv cc functionality. during power up, ensur e that the following conditions are met to guaranty p.o.r. and lv cc operability. 1. "sda='h'" and "scl='l' or 'h'". 2. follow the recommended conditions of tr, toff, vbot so that p.o.r. will be activated during power up. toff tr vbot 0 fig.52 v cc rising wavefrom v cc tr toff vbot below 10ms above 10ms below 0.3v below 100ms above 10ms below 0.2v recommended conditions of tr, toff, vbot 3. prevent sda and scl from being "hi-z". in case that condition 1. and/or 2. cannot be met, take following actions. a if unable to keep condition 1 (sda is "low" during power up) make sure that sda and scl are "high" as in the figure below. tlow tsu:dat tdh a fter vcc becomes stable scl v cc sda fig.53 scl="h" and sda="l" tsu:dat a fter vcc becomes stable fig.54 scl="l" and sda="l" b if unable to keep condition 2 after the power stabilizes, execute software reset. (see page 9,10) c if unable to keep either condition 1 or 2 follow instruction a first, then b lv cc circuit the lv cc circuit prevents write operation at low voltage and prevents inadvertent writi ng. a voltage below the lv cc voltage (1.2v typ.) prohibits write operation. v cc noise bypass capacitor noise and surges on the power line may cause abnormal fu nction. it is recommended that bypass capacitors (0.1 f) be attached between v cc and gnd externally. cautions on use 1) descrived numeric values and data are design repr esentative values, and the values are not guaranteed. 2) we believe that application circuit examples are recomm endable, however, in actual use, confirm characteristics further sufficiently. in the case of us e by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition char acteristics and fluctuations of external parts and our lsi. 3) absolute maximum ratings if the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperat ure exceeding the absolute maximum ratings. in the case of fear exceeding the absolute maximum ratings, take physica l safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. 4) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that each terminal voltage is lower than that of gnd terminal. 5) heat design in consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. 6) terminal to terminal short circuit and wrong packaging when to package lsi on to a board, pay sufficient attention to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of short circuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. 7) use in a strong electromagnetic field may cause malfunction, therfore, evaluate design sufficiently.
19/19 package type fvt:tssop-b8 nux:vson008x2030 e2:reel shape emboss taping tr: reel shape emboss taping b 02=2k r 3 4 e 0 2 w e 2 f v t selection of order type package specifications unit:mm ) tape quantity direction of feed embossed carer tape 2500pcs e2 (pin 1is at the upper left when holding the reel with the left hand while pulling the tape out towards the right) reel direction of feed pin 1 1234 1234 1234 1234 1234 1234 1234 1234 please order in multiples of the minimum quantity catalog no.05t325be '05.10 rohm c 1000 tsu rohm type bus type product type capacity double cell package specifications 5 4 8 1 0.1 6.4 0.3 4.4 0.2 3.0 0.2 0.22 0.1 1.15 0.1 0.65 (0.52) 0.15 0.1 0.3min. 0.1 vson008x2030 tape quantity direction of feed embossed carrier tape 4000pcs (the direction is the 1pin of product is at the upper light when you hold reel on the left hand and you pull out the tape on the right hand) tr when you order , please order in times the amount of package quantity. (unit:mm) reel direction of feed 1pin tssop-b8
notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. appendix1-rev2.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / eupope / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2007 rohm co.,ltd. the products listed in this document are designed to be used with ordinary electronic equipment or de vices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. it is our top priority to supply products with the utmost quality and reliability. however, there is always a chance of failure due to unexpected factors. therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. rohm cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the notes specified in this catalog. 21, saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix

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